Figure 12.26 Data Re-Transfer Operation In Sci Transmission Mode; Figure 12.27 Tend Flag Set Timing During Transmission - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer
Hide thumbs Also See for H8SX/1520 Series:
Table of Contents

Advertisement

Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
TDRE
Transfer from TDR to TSR
TEND
FER/ERS

Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode

Note that the TEND flag is set in different timings depending on the GM bit setting in SMR.
Figure 12.27 shows the TEND flag set timing.
I/O data
TXI
(TEND interrupt)
GM = 0
GM = 1
[Legend]
Ds:
D0 to D7: Data bits
Dp:
DE:
Downloaded from
Elcodis.com
electronic components distributor
nth transfer frame
[1]
Ds
D0
D1
Start bit
Parity bit
Error signal

Figure 12.27 TEND Flag Set Timing during Transmission

Section 12 Serial Communication Interface (SCI)
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
[2]
D2
D3
D4
D5
D6
12.5 etu
11.0 etu
Rev. 3.00 Mar. 14, 2006 Page 435 of 804
(n + 1) th
transfer frame
(DE)
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
[4]
[3]
D7
Dp
DE
Guard time
REJ09B0104-0300

Advertisement

Table of Contents
loading

Table of Contents