Table 9.24 Tiorl_0 - Renesas H8SX/1520 Series Hardware Manual

Table 9.24 TIORL_0

Bit 3 Bit 2
IOC3 IOC2
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 1
[Legend]
X: Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and Pφ/1 is used as the
TCNT_1 counter clock, this setting is ignored and an input capture interrupt is not
generated.
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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Bit 1 Bit 0 TGRC_0
IOC1 IOC0 Function
0 0 Output
compare
0 1
register*
1 0
1 1
0 0
0 1
1 0
1 1
0 0 Input
capture
register*
0 1
1 X
X X
Section 9 16-Bit Timer Pulse Unit (TPU)
Description
TIOCC0 Pin Function
Output disabled
Initial output is 0 output
2
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCC0 pin
Input capture at rising edge
2
Capture input source is TIOCC0 pin
Input capture at falling edge
Capture input source is TIOCC0 pin
Input capture at both edges
Capture input source is channel 1/count clock
1
Input capture* at TCNT_1 count-up/count-down
Rev. 3.00 Mar. 14, 2006 Page 283 of 804
REJ09B0104-0300