Notes On Input Clock Frequency; Figure 18.7 Connection Example Of Bypass Capacitor - Renesas H8SX/1500 Series Hardware Manual

C
1

Figure 18.7 Connection Example of Bypass Capacitor

18.5.4

Notes on Input Clock Frequency

The frequency of the input clock is multiplied in the PLL circuit by a factor of 8. To reduce noises,
a lower frequency ranging of 4 to 9 MHz is recommended.
VCL (41)
1
*
VSS (39)
VCC (22)
2
CB*
VSS (20)
Note: Numbers in parenthesis are pin numbers.
1. A 0.1-µF capacitor should be used here.
2. CB is a laminated ceramic capacitor.
This LSI
VCC (68)
CB*
VSS (71)
VCC (54)
CB*
VSS (52)
Rev. 3.00 Mar. 14, 2006 Page 669 of 804
Section 18 Clock Pulse Generator
2
2
REJ09B0104-0300