Clock Timing; Figure 21.2 System Bus Clock Timing; Table 21.4 Clock Timing - Renesas H8SX/1520 Series Hardware Manual

21.3.1

Clock Timing

Table 21.4 Clock Timing

Conditions: V
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rising time
Clock falling time
Oscillation settling time after
reset (crystal)
Oscillation settling time after
leaving software standby mode
(crystal)
External clock output delay
settling time
External clock input low pulse
width
External clock input high pulse
width
External clock rising time
External clock falling time
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= 4.5 V to 5.5 V, AV
CC
V = AV = 0 V, Iφ = 8 to 40 MHz, Pφ = 8 to 35 MHz,
SS SS
T = –40°C to +85°C (wide-range specifications)
a
Symbol
t
cyc
t
CH
t
CL
t
Cr
t
Cf
t
OSC1
t
OSC2
t
DEXT
T
EXL
T
EXH
T
EXr
T
EXf
Iφ

Figure 21.2 System Bus Clock Timing

= 4.5 V to 5.5 V, AV
CC0
Min. Max.
25 125

5

5

5

5

20

10

2

45

45

5

5
t
cyc
t t
CH Cf
t t
CL Cr
Section 21 Electrical Characteristics
= 4.5 V to 5.5 V,
CC1
Unit. Test Conditions
ns Figure 21.2
ns
ns
ns
ns
ms Figure 21.4
ms Figure 21.3
ms Figure 21.4
ns Figure 21.5
ns External clock
input frequency =
4 to 9 MHz
ns
ns
Rev. 3.00 Mar. 14, 2006 Page 765 of 804
REJ09B0104-0300