Transmit Wait Register (Txpr) - Renesas H8SX/1520 Series Hardware Manual

13.3.5

Transmit Wait Register (TXPR)

TXPR makes transmit messages stored in mailboxes enter the transmit wait state (CAN bus
arbitration wait).
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
15 TXPR7
14 TXPR6
13
TXPR5
12 TXPR4
11 TXPR3
10 TXPR2
9 TXPR1

8
7 TXPR15
6 TXPR14
5 TXPR13
4 TXPR12
3 TXPR11
2 TXPR10
1 TXPR9
0 TXPR8
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15 14
TXPR7 TXPR6 TXPR5
0 0
R/W R/W R/W
7 6
TXPR15 TXPR14 TXPR13
0 0
R/W R/W R/W
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 13 Controller Area Network (HCAN)
13 12 11
TXPR4 TXPR3
0 0 0
R/W R/W
5 4 3
TXPR12 TXPR11
0 0 0
R/W R/W
R/W Description
R/W These bits set a transmit wait (CAN bus arbitration
wait) for the corresponding mailboxes 1 to 15.
R/W
When TXPRn (n = 1 to 15) is set to 1, the
R/W
message in mailbox n becomes the transmit wait
state.
R/W
[Clearing conditions]
R/W
Completion of message transmission
R/W
Completion of transmission cancellation
R/W
Bit 8 is reserved. This is a read-only bit and cannot
R
be modified.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10 9
TXPR2 TXPR1
0 0
R/W R/W
2 1
TXPR10 TXPR9
0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 459 of 804
REJ09B0104-0300
8
—
1
R
0
TXPR8
0
R/W