Block Diagram; Figure 1.1 Block Diagram Of H8Sx/1527 - Renesas H8SX/1500 Series Hardware Manual

Section 1 Overview
1.2

Block Diagram

RAM
ROM
H8SX
CPU
Clock pulse
generator
[Legend]
CPU: Central processing unit
DMAC: DMA controller
BSC: Bus controller
WDT: Watchdog timer
TPU: 16-bit timer pulse unit
Rev. 3.00 Mar. 14, 2006 Page 2 of 804
REJ09B0104-0300
Interrupt
controller
BSC
DMAC
× 4 channels
PPG: Programmable pulse generator
SCI:
HCAN: Controller area network
SSU:

Figure 1.1 Block Diagram of H8SX/1527

WDT
TPU (unit 0)
× 6 channels
TPU (unit 1)
× 6 channels
PPG
SCI × 2 channels
HCAN
SSU × 3 channels
A/D (unit 0)
× 8 channels
A/D (unit 1)
× 8 channels
On-chip debugging
function for E10A
Serial communication interface
Synchronous communication unit
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port A
Port D
Port H
Port J
Port K