Scs Pin Control And Conflict Error; Figure 14.10 Conflict Error Detection Timing (Before Transfer); Figure 14.11 Conflict Error Detection Timing (After Transfer End) - Renesas H8SX/1520 Series Hardware Manual

Section 14 Synchronous Serial Communication Unit (SSU)

SCS Pin Control and Conflict Error

14.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. The detection
period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends.
When a low level signal is input to the SCS pin within the period, a conflict error occurs. At this
time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
before resuming the transmission or reception.
External input to SCS
Internal-clocked SCS
MSS
Internal signal for
transfer enable
CE
SCS output
Pφ
SCS
MSS
Internal signal for
transfer enable
CE

Figure 14.11 Conflict Error Detection Timing (After Transfer End)

Rev. 3.00 Mar. 14, 2006 Page 538 of 804
REJ09B0104-0300
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(Hi-Z)

Figure 14.10 Conflict Error Detection Timing (Before Transfer)

Transfer
Data written
to SSTDR
Conflict error
detection period
Worst time for
internally clocking SCS
end
Conflict error detection period
(Hi-Z)