Phase Counting Mode; Table 9.34 Clock Input Pins In Phase Counting Mode - Renesas H8SX/1520 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.6

Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 9.34 shows the correspondence between external clock pins and channels.

Table 9.34 Clock Input Pins in Phase Counting Mode

Channels
When channel 1 or 5 is set to phase counting mode
When channel 2 or 4 is set to phase counting mode
Rev. 3.00 Mar. 14, 2006 Page 318 of 804
REJ09B0104-0300
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External Clock Pins
A-Phase B-Phase
TCLKA TCLKB
TCLKC TCLKD