Dma Address Control Register (Dacr) - Renesas H8SX/1500 Series Hardware Manual

7.2.7

DMA Address Control Register (DACR)

DACR specifies the operating mode and transfer method.
Bit 31
Bit Name AMS
Initial Value 0
R/W R/W
Bit 23
Bit Name —
Initial Value 0
R/W R
Bit 15
Bit Name SARIE
Initial Value 0
R/W R/W
Bit 7
Bit Name DARIE
Initial Value 0
R/W R/W
Bit Bit Name
31 AMS
30 DIRS
29 to 27 
30 29
DIRS —
0 0
R/W R
22 21
— SAT1
0 0
R R/W
14 13
— —
0 0
R R
6 5
— —
0 0
R R
Initial
Value R/W
0 R/W
0 R/W
0 R/W
28 27
— —
0 0
R R
20 19
SAT0 —
0 0
R/W R
12 11
SARA4 SARA3
0 0
R/W R/W
4 3
DARA4 DARA3
0 0
R/W R/W
Description
Address Mode Select
Selects address mode from single or dual address
mode. In single address mode, the DACK pin is enabled
according to the DACKE bit.
0: Dual address mode
1: Single address mode
Single Address Direction Select
Specifies the data transfer direction in single address
mode. This bit s ignored in dual address mode.
0: Specifies DSAR as source address
1: Specifies DDAR as destination address
Reserved
These are read-only bits and cannot be modified.
Rev. 3.00 Mar. 14, 2006 Page 151 of 804
Section 7 DMA Controller (DMAC)
26 25
RPTIE ARS1 ARS0
0 0
R/W R/W
18 17
— DAT1
0 0
R R/W
10 9
SARA2 SARA1 SARA0
0 0
R/W R/W
2 1
DARA2 DARA1 DARA0
0 0
R/W R/W
REJ09B0104-0300
24
0
R/W
16
DAT0
0
R/W
8
0
R/W
0
0
R/W