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Section 21 Electrical Characteristics
Table 21.6 Timing of On-Chip Peripheral Modules (2)
Conditions: V
= 4.5 V to 5.5 V, AV
CC
V
= AV
SS
T
= –40°C to +85°C (wide-range specifications)
a
Item
HCAN*
Transmit data delay time
Receive data setup time
Receive data hold time
SSU
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rising time
Clock falling time
Data input setup time
Data input hold time
SCS setup time
SCS hold time
Data output delay time
Data output hold time
Consecutive transmit
delay time
Rev. 3.00 Mar. 14, 2006 Page 770 of 804
REJ09B0104-0300
= 4.5 V to 5.5 V, AV
CC0
= 0 V, Pφ = 8 to 20 MHz,
SS
Symbol
t
HTXD
t
HRXS
t
HRXH
t
Master
SUcyc
Slave
t
Master
HI
Slave
t
Master
LO
Slave
t
RISE
t
FALL
t
Master
SU
Slave
t
Master
H
Slave
t
Master
LEAD
Slave
t
Master
LAG
Slave
t
Master
OD
Slave
t
Master
OH
Slave
t
Master
TD
Slave
= 4.5 V to 5.5 V,
CC1
Min.
Max.
Unit
100
ns
100
ns
100
ns
4
256
t
cyc
4
256
80
ns
80
80
ns
80
20
ns
20
ns
25
ns
30
10
ns
10
2.5
t
cyc
2.5
2.5
t
cyc
2.5
40
ns
40
30
ns
30
2.5
t
cyc
2.5
Test Conditions
Figure 21.16
Figure 21.17
Figure 21.18
Figure 21.19
Figure 21.20
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