Interrupt Register (Irr) - Renesas H8SX/1500 Series Hardware Manual

13.3.11 Interrupt Register (IRR)

IRR is an interrupt status flag register.
Bit 15
Bit Name IRR7
Initial Value 0
R/W R/(W)*
Bit 7
Bit Name —
Initial Value 0
R/W —
Note: * Only 1 can be written to these bits, to clear the flags.
Bit Bit Name
15 IRR7
14 13
IRR6 IRR5
0 0
R/(W)* R/(W)* R/(W)*
6 5
— —
0 0
— — R/(W)*
Initial
Value R/W
0 R/(W)*
Section 13 Controller Area Network (HCAN)
12 11
IRR4 IRR3 IRR2
0 0
R/(W)*
4 3
IRR12 —
0 0
—
Description
Overload Frame Interrupt Flag
Status flag indicating that the HCAN transmits the
overload frame.
[Setting condition]
When an overload frame is transmitted in error
active/passive state
[Clearing condition]
Writing 1
(When the CPU is used to clear this flag by
writing 1 while the corresponding interrupt is
enabled, be sure to read the flag after writing 1 to
it.)
Rev. 3.00 Mar. 14, 2006 Page 465 of 804
10 9 8
IRR1 IRR0
0 0 1
R R R/(W)*
2 1 0
— IRR9 IRR8
0 0 0
— R R/(W)*
REJ09B0104-0300