Figure 9.2 Block Diagram Of Tpu (Unit 1) - Renesas H8SX/1520 Series Hardware Manual

Input/output pins
Channel 9:
Channel 10:
Channel 11:
Internal clock:
External clock:
Input/output pins
Channel 6:
Channel 7:
Channel 8:
[Legend]
TSTRB:
TSYRB:
TCR:
TMDR:
TIOR (H, L): Timer I/O control registers (H, L)
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TIOCA9
TIOCB9
TIOCC9
TIOCD9
TIOCA10
TIOCB10
TIOCA11
TIOCB11
Clock input
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
TCLKE
TCLKF
TCLKG
TCLKH
TIOCA6
TIOCB6
TIOCC6
TIOCD6
TIOCA7
TIOCB7
TIOCA8
TIOCB8
Timer start register
Timer synchronous register
Timer control register
Timer mode register

Figure 9.2 Block Diagram of TPU (Unit 1)

Section 9 16-Bit Timer Pulse Unit (TPU)
TIER: Timer interrupt enable register
TSR: Timer status register
TGR (A, B, C, D): Timer general registers (A, B, C, D)
TCNT: Timer counter
Rev. 3.00 Mar. 14, 2006 Page 257 of 804
Interrupt request signals
Channel 9: TGI9A
TGI9B
TGI9C
TGI9D
TCI9V
Channel 10: TGI10A
TGI10B
TCI10V
TCI10U
Channel 11: TGI11A
TGI11B
TCI11V
TCI11U
Internal data bus
Interrupt request signals
Channel 6: TGI6A
TGI6B
TGI6C
TGI6D
TCI6V
Channel 7: TGI7A
TGI7B
TCI7V
TCI7U
Channel 8: TGI8A
TGI8B
TCI8V
TCI8U
REJ09B0104-0300