Figure 12.32 Clock Stop And Restart Procedure - Renesas H8SX/1520 Series Hardware Manual

At power-on and transitions to/from software standby mode, use the following procedure to secure
the appropriate clock duty cycle.
• At power-on
To secure the appropriate clock duty cycle simultaneously with power-on, use the following
procedure.
1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a
pull-up or pull-down resistor.
2. Fix the SCK pin to the specified output using the CKE1 bit in SCR.
3. Set SMR and SCMR to enable smart card interface mode.
Set the CKE0 bit in SCR to 1 to start clock output.
• At mode switching
 At transition from smart card interface mode to software standby mode
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK
pin to the values for the output fixed state in software standby mode.
2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously,
set the CKE1 bit to the value for the output fixed state in software standby mode.
3. Write 0 to the CKE0 bit in SCR to stop the clock.
4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the
specified level with the duty cycle retained.
5. Make the transition to software standby mode.
 At transition from smart card interface mode to software standby mode
6. Clear software standby mode.
7. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the
appropriate duty cycle is then generated.
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Normal operation
[1] [2] [3] [4] [5]

Figure 12.32 Clock Stop and Restart Procedure

Section 12 Serial Communication Interface (SCI)
Software
Normal operation
standby
[6] [7]
Rev. 3.00 Mar. 14, 2006 Page 439 of 804
REJ09B0104-0300