Figure 7.30 Example Of Transfer In Normal Transfer Mode Activated By Dreq Low Level - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)
Activation Timing by DREQ Low Level
(5)
Figure 7.30 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
Bus released
Bφ
DREQ
Address bus
DMA
Wait
operation
Request
Channel
Min. of 3 cycles
[1]
[2]
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
[1]
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 7.30 Example of Transfer in Normal Transfer Mode Activated
Rev. 3.00 Mar. 14, 2006 Page 188 of 804
REJ09B0104-0300
DMA read DMA write
cycle cycle
Transfer Transfer
source destination
Read Write Wait
Duration of transfer
request disabled
[3]
Transfer request enable resumed
by DREQ Low Level
DMA read
Bus released
cycle
Transfer
source
Read
Duration of transfer
request disabled
Request
Min. of 3 cycles
[5] [6]
[4]
DMA write
Bus released
cycle
Transfer
destination
Write Wait
[7]
Transfer request enable resumed