5.3
Register Descriptions
The interrupt controller has the following registers.
• Interrupt control register (INTCR)
• CPU priority control register (CPUPCR)
• Interrupt priority registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO,
IPRQ, and IPRR)
• IRQ enable register (IER)
• IRQ sense control registers H and L (ISCRH, ISCRL)
• IRQ status register (ISR)
• Software standby release IRQ enable register (SSIER)
5.3.1
Interrupt Control Register (INTCR)
INTCR selects the interrupt control mode, and the detected edge for NMI.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
7, 6
5
INTM1
4
INTM0
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7
6
5
—
—
INTM1
0
0
0
R
R
R/W
Initial
Value
R/W
All 0
R
0
R/W
0
R/W
4
3
INTM0
NMIEG
0
0
R/W
R/W
Description
Reserved
These are read-only bits and cannot be modified.
Interrupt Control Select Mode 1 and 0
These bits select either of two interrupt control modes
for the interrupt controller.
00: Interrupt control mode 0
Interrupts are controlled by I bit in CCR.
01: Setting prohibited.
10: Interrupt control mode 2
Interrupts are controlled by bits I2 to I0 in EXR, and
IPR.
11: Setting prohibited.
Rev. 3.00 Mar. 14, 2006 Page 89 of 804
Section 5 Interrupt Controller
2
1
0
—
—
—
0
0
0
R
R
R
REJ09B0104-0300