Main Revisions And Additions In This Edition - Renesas H8SX/1500 Series Hardware Manual

Main Revisions and Additions in this Edition

Item
Section 3 MCU Operating Modes
3.2.2 System Control Register
(SYSCR)
3.4.1 Address Map (Advanced
Mode)
Section 4 Exception Handling
4.9 Usage Note
Figure 4.3 Operation when SP
Value Is Odd
Section 5 Interrupt Controller
5.3.7 Software Standby Release
IRQ Enable Register (SSIER)
5.6.5 DMAC Activation by
Interrupt
(1) Selection of Interrupt Sources
Page Revision (See Manual for Details)
69 Deleted
SYSCR controls MAC saturation operation bus with
mode for instruction fetch, and selects enables/disables
the on-chip RAM and the flash memory control
registers.
72 Amended
86 Amended
TRAPA instruction executed
102 Amended
These bits select the IRQn pins used to leave software
standby mode (n = 14 to 0).
119 Added
The selected activation source is input to the DMAC
through the select circuit. When transfer by an on-chip
module interrupt is enabled (DTF1 = 1, DTF0 = 0, and
DTE = 1) and the DTA bit in DMDR is set to 1, the
interrupt source selected for the DMAC activation
source is controlled by the DMAC and cannot be used
as a DTC activation source or CPU interrupt source.
Amended
When the same interrupt source is set as both the
DMAC activation source and CPU interrupt source, the
DMAC must be given priority over the CPU. If the
IPSETE bit in CPUPCR is set to 1, the priority is
determined according to the IPR setting. Therefore, the
CPUP setting or the IPR setting corresponding to the
interrupt source must be set to lower than or equal to
the DMAP settings. If the CPU is given priority, the
DMAC may not be activated and the data transfer may
be performed.
On-chip ROM
(256 kbytes)
H'040000
Reserved
H'FF9000
On-chip RAM
(12 kbytes)
Rev. 3.00 Mar. 14, 2006 Page 783 of 804
REJ09B0104-0300