Figure 7.27 Example Of Transfer In Normal Transfer Mode By Burst Access - Renesas H8SX/1500 Series Hardware Manual

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Normal Transfer Mode (Burst Mode)
In burst mode, one byte, one word, or one longword of data continues to be transferred until the
transfer end condition is satisfied.
When a burst transfer starts, a transfer request from a channel having priority is suspended until
the burst transfer is completed.
In figure 7.27, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by burst access.
DMA
read cycle
Bφ
Address
bus
RD
HHWR,
High
HLWR
LHWR,
LLWR
TEND
Bus
released

Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access

DMA DMA
write cycle read cycle
Burst transfer
Section 7 DMA Controller (DMAC)
DMA DMA
write cycle read cycle
Last transfer cycle
Rev. 3.00 Mar. 14, 2006 Page 185 of 804
DMA
write cycle
Bus
released
REJ09B0104-0300