Relationship Among Dmac And Other Bus Masters; Cpu Priority Control Function Over Dmac - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)
(7)
Transfer End by Address Error
When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit
in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is
forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0
and then set the DTE bits for the channels.
The transfer end timing after an address error is the same as that after an NMI interrupt.
(8)
Transfer End by Hardware Standby Mode or Reset
The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA
transfer is not guaranteed.
7.6

Relationship among DMAC and Other Bus Masters

7.6.1

CPU Priority Control Function Over DMAC

The CPU priority control function over DMAC can be used according to the CPU priority control
register (CPUPCR) setting. For details, see section 5.7, CPU Priority Control Function Over
DMAC.
The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for
each channel.
The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to
CPUP0 is updated according to the exception handling priority.
If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority
over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not
activated. When another channel has priority over or the same as the CPU, a transfer request is
received regardless of the priority between channels and the transfer is activated.
If the priority level of the transfer request masked by the CPU priority control function is changed
or the CPU priority is changed, the transfer request may be received and the transfer is started.
When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority. Transfer requests
masked are suspended. If a transfer request is suspended, it is cleared by clearing the DTE bit to 0.
Rev. 3.00 Mar. 14, 2006 Page 198 of 804
REJ09B0104-0300