Ss Receive Data Registers 0 To 3 (Ssrdr0 To Ssrdr3); Table 14.2 Correspondence Between Dats Bit Setting And Sstdr - Renesas H8SX/1500 Series Hardware Manual

Section 14 Synchronous Serial Communication Unit (SSU)

Table 14.2 Correspondence Between DATS Bit Setting and SSTDR

SSTDR 00
0 Valid
1 Invalid
2 Invalid
3 Invalid
14.3.8

SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)

SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Be
sure not to access invalid SSRDRs.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR
function as a double buffer in this way, consecutive receive operations can be performed.
Read SSRDR after confirming that the RDRF bit in SSSR is set to 1.
SSRDR is a read-only register, therefore, cannot be written to by the CPU.
Rev. 3.00 Mar. 14, 2006 Page 524 of 804
REJ09B0104-0300
DATS[1:0] (SSCRL[1:0])
01 10
Valid Valid
Valid Valid
Invalid Valid
Invalid Valid
11 (Setting Invalid)
Invalid
Invalid
Invalid
Invalid