Interrupt Register (Irr) - Renesas H8SX/1520 Series Hardware Manual

13.3.11 Interrupt Register (IRR)

IRR is an interrupt status flag register.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * Only 1 can be written to these bits, to clear the flags.
Bit Bit Name
15 IRR7
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15 14
IRR7 IRR6 IRR5
0 0
R/(W)* R/(W)* R/(W)*
7 6
— —
0 0
— —
Initial
Value
0
Section 13 Controller Area Network (HCAN)
13 12 11
IRR4 IRR3
0 0 0
R/(W)* R/(W)*
5 4 3
— IRR12 —
0 0 0
— R/(W)* —
R/W Description
R/(W)* Overload Frame Interrupt Flag
Status flag indicating that the HCAN transmits the
overload frame.
[Setting condition]
When an overload frame is transmitted in error
active/passive state
[Clearing condition]
Writing 1
(When the CPU is used to clear this flag by
writing 1 while the corresponding interrupt is
enabled, be sure to read the flag after writing 1 to
it.)
10 9
IRR2 IRR1
0 0
R R
2 1
— IRR9
0 0
— R
Rev. 3.00 Mar. 14, 2006 Page 465 of 804
REJ09B0104-0300
8
IRR0
1
R/(W)*
0
IRR8
0
R/(W)*