Table 21.6 Timing Of On-Chip Peripheral Modules (2) - Renesas H8SX/1520 Series Hardware Manual

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Section 21 Electrical Characteristics

Table 21.6 Timing of On-Chip Peripheral Modules (2)

Conditions: V
V
T
HCAN*
Transmit data delay time
Receive data setup time
Receive data hold time
SSU
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rising time
Clock falling time
Data input setup time
Data input hold time
SCS setup time
SCS hold time
Data output delay time
Data output hold time
Consecutive transmit
delay time
Rev. 3.00 Mar. 14, 2006 Page 770 of 804
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= 4.5 V to 5.5 V, AV
CC
= AV
= 0 V, Pφ = 8 to 20 MHz,
SS
SS
= –40°C to +85°C (wide-range specifications)
a
Item
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
= 4.5 V to 5.5 V, AV
CC0
Symbol
Min.
t
HTXD
t
100
HRXS
t
100
HRXH
t
4
SUcyc
4
t
80
HI
80
t
80
LO
80
t
RISE
t
FALL
t
25
SU
30
t
10
H
10
t
2.5
LEAD
2.5
t
2.5
LAG
2.5
t
OD
t
30
OH
30
t
2.5
TD
2.5
= 4.5 V to 5.5 V,
CC1
Max.
Unit
Test Conditions
100
ns
Figure 21.16
ns
ns
256
t
Figure 21.17
cyc
256
Figure 21.18
ns
Figure 21.19
Figure 21.20
ns
20
ns
20
ns
ns
ns
t
cyc
t
cyc
40
ns
40
ns
t
cyc

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