Figure 7.5 Example Of Signal Timing In Single Address Mode; Figure 7.6 Operations In Single Address Mode - Renesas H8SX/1520 Series Hardware Manual

Transfer from external memory to external device with DACK
Transfer from external device with DACK to external memory
Address T
Address B
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DMA cycle
Bφ
Address bus
RD
WR
DACK
Data bus
TEND
DMA cycle
Bφ
Address bus
RD
WR
DACK
Data bus
TEND

Figure 7.5 Example of Signal Timing in Single Address Mode

Figure 7.6 Operations in Single Address Mode

Address for external memory space
DSAR
RD signal for external memory space
Data output by external memory
Address for external memory space
DDAR
WR signal for external memory space
Data output by external device with DACK
Transfer
Section 7 DMA Controller (DMAC)
DACK
Rev. 3.00 Mar. 14, 2006 Page 161 of 804
REJ09B0104-0300