Operation; Transfer Clock; Relationship Of Clock Phase, Polarity, And Data; Figure 14.2 Relationship Of Clock Phase, Polarity, And Data - Renesas H8SX/1500 Series Hardware Manual

Section 14 Synchronous Serial Communication Unit (SSU)
14.4

Operation

14.4.1

Transfer Clock

A transfer clock can be selected from eight internal clocks and an external clock. When using this
module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS
bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When
transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output
from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an
input pin.
14.4.2

Relationship of Clock Phase, Polarity, and Data

The relationship of clock phase, polarity, and transfer data depends on the combination of the
CPOS and CPHS bits in SSMR. Figure 14.2 shows the relationship. When SSUMS = 1, the CPHS
setting is invalid although the CPOS setting is valid.
Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data
is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the
LSB.
(1) When CPHS = 0
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
(2) When CPHS = 1
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO

Figure 14.2 Relationship of Clock Phase, Polarity, and Data

Rev. 3.00 Mar. 14, 2006 Page 526 of 804
REJ09B0104-0300
Bit 0 Bit 1 Bit 2
Bit 0 Bit 1 Bit 2 Bit 3
Bit 3 Bit 4 Bit 5 Bit 6
Bit 4 Bit 5 Bit 6
Bit 7
Bit 7