Master Control Register (Mcr) - Renesas H8SX/1500 Series Hardware Manual

13.3.1

Master Control Register (MCR)

MCR controls the HCAN.
Bit 7
Bit Name MCR7
Initial Value 0
R/W R/W
Bit Bit Name
7 MCR7

6
5 MCR5

4, 3
2 MCR2
1 MCR1
6 5
— MCR5
0 0
R R/W
Initial
Value R/W
0 R/W
0 R
0 R/W
All 0 R
0 R/W
0 R/W
Section 13 Controller Area Network (HCAN)
4 3
— — MCR2
0 0
R R R/W
Description
HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically
exits HCAN sleep mode on detection of CAN bus
operation.
Reserved
This is a read-only bit and cannot be modified.
HCAN Sleep Mode
When this bit is set to 1, the HCAN enters HCAN
sleep mode. When this bit is cleared to 0, HCAN
sleep mode is released.
Reserved
These are read-only bits and cannot be modified.
Message Transmission Method
0: Transmission order determined by message
identifier priority
1: Transmission order determined by mailbox
(buffer) number priority (TXPR1 > TXPR15)
Halt Request
When this bit is set to 1, the HCAN enters HCAN
HALT mode. When this bit is cleared to 0, HCAN
HALT mode is released.
Rev. 3.00 Mar. 14, 2006 Page 453 of 804
2 1 0
MCR1 MCR0
0 0 1
R/W R/W
REJ09B0104-0300