Bφ Clock Output Control; Table 19.3 Bφ Pin (Pa7) State In Each Processing State - Renesas H8SX/1520 Series Hardware Manual

19.8 Bφ Clock Output Control
Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for
the corresponding PA7 pin.
Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When
bit PSTOP1 is set to 1, the Bφ clock output stops at the end of the bus cycle, and the Bφ clock
output goes high. When DDR for the PA7 pin is cleared to 0, the Bφ clock output is disabled and
the pin becomes an input port.
Disabling Bφ output can reduce electromagnetic interference (EMI). Take it into consideration for
design of the user system board.
Tables 19.3 shows the states of the Bφ pin in each processing state.
Table 19.3 Bφ Pin (PA7) State in Each Processing State
Register Setting Value
DDR
0
1
1
1
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PSTOP1 POSEL1
X X
0 0
0 1
1 X
Normal
Operating
State Sleep Mode
Hi-Z Hi-Z
Bφ output Bφ output
Setting Setting
prohibited prohibited
High High
Section 19 Power-Down Modes
All-Module- Software Standby Mode
Clock-Stop
Mode OPE = 0
Hi-Z Hi-Z
Bφ output High
Setting Setting
prohibited prohibited
High High
Rev. 3.00 Mar. 14, 2006 Page 685 of 804
REJ09B0104-0300
OPE = 1
Hi-Z
High
Setting
prohibited
High