Interrupt Sources; External Interrupts - Renesas H8SX/1520 Series Hardware Manual

5.4

Interrupt Sources

5.4.1

External Interrupts

There are sixteen external interrupts: NMI and IRQ14 to IRQ0. These interrupts can be used to
leave software standby mode.
(1)
NMI Interrupts:
Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by
the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.
The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on
the NMI pin.
When an NMI interrupt is generated, the interrupt controller determines that an error has occurred,
and performs the following procedure.
• Sets the ERRF bit in DMDR_0 to 1.
• Clears the DTE bits for all the channels of the DMAC and forcibly halts transfer.
(2)
IRQn Interrupts:
An IRQn interrupt is requested by a signal input on pins IRQ14 to IRQ0. IRQn (n = 14 to 0) have
the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, on pins IRQn.
• Enabling or disabling of interrupt requests IRQn can be selected by IER.
• The interrupt priority can be set by IPR.
• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by
software. The bit manipulation instructions or memory operation instructions should be used to
clear the flag in ISR.
Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register
settings, and does not change regardless of the output setting. However, when a pin is used as an
external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing
the corresponding DDR bit to 0.
A block diagram of interrupts IRQn is shown in figure 5.2.
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Section 5 Interrupt Controller
Rev. 3.00 Mar. 14, 2006 Page 103 of 804
REJ09B0104-0300