Figure 13.8 Detailed Description Of One Bit; Table 13.2 Limits For The Settable Value - Renesas H8SX/1520 Series Hardware Manual

(2)
Bit Rate and Bit Timing Settings
The bit rate and bit timing settings are made in the bit configuration register (BCR). Settings
should be made such that all CAN controllers connected to the CAN bus have the same baud rate
and bit width. The 1-bit time consists of the total of the settable time quanta (tq).
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, BSP, and
SJW) are shown in table 13.2.

Table 13.2 Limits for the Settable Value

Name
Time segment 1
Time segment 2
Baud rate prescaler
Bit sample point
Re-synchronization jump width
Notes: 1. SJW is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
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1-bit time (8–25 time quanta)
SYNC_SEG PRSEG
1 time quanta

Figure 13.8 Detailed Description of One Bit

Section 13 Controller Area Network (HCAN)
PHSEG1
Time segment 1 (TSEG1)
4 to 16 time quanta
Abbreviation
TSEG1
TSEG2
BRP
BSP
1
SJW*
Rev. 3.00 Mar. 14, 2006 Page 487 of 804
PHSEG2
Time segment 2
(TSEG2)
2 to 8 time quanta
Min. Value Max. Value
2
B'0011* B'1111
3
B'001* B'111
B'000000 B'111111
B'0 B'1
B'00 B'11
REJ09B0104-0300