Receive Complete Register (Rxpr) - Renesas H8SX/1520 Series Hardware Manual

13.3.9

Receive Complete Register (RXPR)

RXPR indicates the normal reception of messages (data frame or remote frame) in mailboxes. For
reception of a remote frame, when a bit in this register is set to 1, the corresponding remote
request register (RFPR) bit is also set to 1 simultaneously.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * Only 1 can be written to these bits, to clear the flags.
Bit Bit Name
15 RXPR7
14 RXPR6
13 RXPR5
12 RXPR4
11 RXPR3
10 RXPR2
9 RXPR1
8 RXPR0
7 RXPR15
6 RXPR14
5 RXPR13
4 RXPR12
3 RXPR11
2 RXPR10
1 RXPR9
0
RXPR8
Note: Only 1 can be written to clear the flag.
*
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15 14
RXPR7 RXPR6 RXPR5
0 0
R/(W)* R/(W)* R/(W)*
7 6
RXPR15 RXPR14 RXPR13
0 0
R/(W)* R/(W)* R/(W)*
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 13 Controller Area Network (HCAN)
13 12 11
RXPR4 RXPR3
0 0 0
R/(W)* R/(W)*
5 4 3
RXPR12 RXPR11
0 0 0
R/(W)* R/(W)*
R/W Description
R/(W)* When the message in mailbox n (n = 1 to 15) has
been received error-free, RXPRn is set to 1.
R/(W)*
[Setting condition]
R/(W)*
Completion of message (data frame or remote
R/(W)*
frame) reception in corresponding mailbox
R/(W)*
[Clearing condition]
R/(W)*
Writing 1
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
10 9
RXPR2 RXPR1
0 0
R/(W)* R/(W)*
2 1
RXPR10 RXPR9
0 0
R/(W)* R/(W)*
Rev. 3.00 Mar. 14, 2006 Page 463 of 804
REJ09B0104-0300
8
RXPR0
0
R/(W)*
0
RXPR8
0
R/(W)*