Table 9.7 Input Clock Edge Selection; Table 9.8 Tpsc2 To Tpsc0 (Channel 0); Table 9.9 Tpsc2 To Tpsc0 (Channel 1) - Renesas H8SX/1520 Series Hardware Manual

Table 9.7
Clock Edge Selection
CKEG1
0
0
1
[Legend]
X: Don't care
Table 9.8
Bit 2
Channel TPSC2
0 0
0
0
0
1
1
1
1
Table 9.9
Bit 2
Channel
TPSC2
1 0
0
0
0
1
1
1
1
Note: This setting is ignored when channel 1 is in phase counting mode.
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Input Clock Edge Selection
CKEG0 Internal Clock
0 Counted at falling edge
1 Counted at rising edge
X Counted at both edges
TPSC2 to TPSC0 (Channel 0)
Bit 1
TPSC1
0
0
1
1
0
0
1
1
TPSC2 to TPSC0 (Channel 1)
Bit 1
TPSC1
0
0
1
1
0
0
1
1
Input Clock
Bit 0
TPSC0 Description
0 Internal clock: counts on Pφ/1
1 Internal clock: counts on Pφ/4
0 Internal clock: counts on Pφ/16
1 Internal clock: counts on Pφ/64
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
0 External clock: counts on TCLKC pin input
1 External clock: counts on TCLKD pin input
Bit 0
Description
TPSC0
0 Internal clock: counts on Pφ/1
1 Internal clock: counts on Pφ/4
0 Internal clock: counts on Pφ/16
1 Internal clock: counts on Pφ/64
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
0 Internal clock: counts on Pφ/256
1 Counts on TCNT2 overflow/underflow
Section 9 16-Bit Timer Pulse Unit (TPU)
External Clock
Counted at rising edge
Counted at falling edge
Counted at both edges
Rev. 3.00 Mar. 14, 2006 Page 267 of 804
REJ09B0104-0300