Cpu Priority Control Register (Cpupcr) - Renesas H8SX/1500 Series Hardware Manual

Section 5 Interrupt Controller
Bit Bit Name
3 NMIEG

2 to 0
5.3.2

CPU Priority Control Register (CPUPCR)

CPUPCR sets whether or not the CPU has priority over the DMAC. The interrupt exception
handling by the CPU can be given priority over that of the DMAC transfer. The priority level of
the DMAC for each channel is set by the DMAC control register.
Bit 7
Bit Name CPUPCE
Initial Value 0
R/W R/W
Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
Bit Bit Name
7 CPUPCE

6 to 4
Rev. 3.00 Mar. 14, 2006 Page 90 of 804
REJ09B0104-0300
Initial
Value R/W
0 R/W
All 0 R
6 5
— —
0 0
R/W R/W
Initial
Value R/W Description
0 R/W CPU Priority Control Enable
Controls the CPU priority control function. Setting this bit
to 1 enables the CPU priority control over the DMAC.
0: CPU always has the lowest priority
1: CPU priority control enabled
All 0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
Description
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of NMI
input
1: Interrupt request generated at rising edge of NMI
input
Reserved
These are read-only bits and cannot be modified.
4 3
— IPSETE
0 0
R/W R/W
2 1
CPUP2 CPUP1 CPUP0
0 0
R/(W)* R/(W)* R/(W)*
0
0