Figure 7.19 Xy Conversion Operation Using Offset Addition In Repeat Transfer Mode - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)
(2)
XY Conversion Using Offset
Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode.
Data 1 Data 9
Data 5
Data 2 Data 10
Data 6
Data 7
Data 3
Data 11
Data 4 Data 8
Data 12
1st transfer
Data 1
Data 5
Address
Offset
Data 9 initialized
Data 13
Data 2
Data 6
Offset
Data 10
Data 14
Data 3
Data 7
Offset
Data 11
Data 15
Data 4
Interrupt
Data 8
request
Data 12
generated
Data 16

Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode

In figure 7.19, the source address side is specified to the repeat area by DACR and the offset
addition is selected. The offset value is set to 4 × data access size (when the data access size is
longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 × data access
size (when the data access size is longword, the repeat size is set to 4 × 4 = 16 bytes, as an
example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address.
A repeat size end interrupt is requested when the repeat size of transfers is completed.
When a transfer starts, the transfer source address is added to the offset every time data is
transferred. The transfer data is written to the destination continuous addresses. When data 4 is
transferred meaning that the repeat size of transfers is completed, the transfer source address
returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end
interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are
written to the address of data 5 by the CPU (when the data access size is longword, write the data
1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when
the transfer is stopped. Accordingly, operations are repeated and the transfer source data is
transposed to the destination area (XY conversion).
Rev. 3.00 Mar. 14, 2006 Page 174 of 804
REJ09B0104-0300
Data 13
1st transfer
2nd transfer
Data 14
Transfer
3rd transfer
Data 15
4th transfer
Data 16
2nd transfer
Transfer source
addresses
changed by CPU
Data 1
Data 5
Data 9
Address
Data 13
initialized
Data 2
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Interrupt
request
Data 16
generated
Data 1
Data 2
Data 3
Data 5 Data 7
Data 6
Data 10 Data 11
Data 9
Data 14
Data 15
Data 13
3rd transfer
Data 1
Transfer
Data 5
Data 9
Data 13
Transfer source
Data 2
addresses
changed by CPU
Data 6
Data 10
Data 14
Data 3
Data 7
Data 11
Data 15
Data 4
Data 8
Data 12
Interrupt
Data 16
request
generated
Data 4
Data 8
Data 12
Data 16
Data 1
Data 2
1st transfer
Data 3
Data 4
Data 5
Data 6
2nd transfer
Data 7
Data 8
Data 9
Data 10
3rd transfer
Data 11
Data 12
Data 13
Data 14
4th transfer
Data 15
Data 16