Figure 12.20 Sample Flowchart Of Simultaneous Serial Transmission And Reception - Renesas H8SX/1520 Series Hardware Manual

Section 12 Serial Communication Interface (SCI)
Note: When switching from transmit or receive operation to
simultaneous transmit and receive operations, first clear the
TE bit and RE bit to 0, then set both these bits to 1
simultaneously.

Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception

Rev. 3.00 Mar. 14, 2006 Page 428 of 804
REJ09B0104-0300
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Initialization
Start transmission/reception
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read ORER flag in SSR
ORER = 1
No
Read RDRF flag in SSR
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear TE and RE bits in SCR to 0
<End>
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
[2]
[2] SCI state check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0. Transition of the
TDRE flag from 0 to 1 can also be
identified by a TXI interrupt.
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to
0. Reception cannot be resumed if
Yes
the ORER flag is set to 1.
[3]
[4] SCI state check and receive data
Error processing
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
[4]
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
[5]
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
However, the TDRE flag is checked
and cleared automatically when the
DMAC is initiated by a transmit data
empty interrupt (TXI) request and
writes data to TDR. Similarly, the
RDRF flag is cleared automatically
when the DMAC is initiated by a
receive data full interrupt (RXI) and
reads data from RDR.