Figure 1.2 Block Diagram Of H8Sx/1525 - Renesas H8SX/1500 Series Hardware Manual

RAM
ROM
H8SX
CPU
Clock pulse
generator
[Legend]
CPU: Central processing unit
DMAC: DMA controller
BSC: Bus controller
WDT: Watchdog timer
TPU: 16-bit timer pulse unit

Figure 1.2 Block Diagram of H8SX/1525

Interrupt
controller
BSC
DMAC
x 4 channels
SCI: Serial communication interface
HCAN: Controller area network
SSU: Synchronous communication unit
WDT
TPU (unit 1)
x 6 channels
SCI x 2 channels
HCAN
SSU x 3 channels
A/D (unit 0) x 8 channels
A/D (unit 1) x 8 channels
On-chip debugging
function for E10A
Rev. 3.00 Mar. 14, 2006 Page 3 of 804
Section 1 Overview
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port A
Port D
Port H
Port J
Port K
REJ09B0104-0300