Dma Offset Register (Dofr) - Renesas H8SX/1520 Series Hardware Manual

7.2.3

DMA Offset Register (DOFR)

DOFR is a 32-bit readable/writable register that specifies the offset to update the source and
destination addresses. Although different values are specified for individual channels, the same
values must be specified for the source and destination sides of a single channel.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
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31 30 29
0 0 0
R/W R/W R/W
23 22 21
0 0 0
R/W R/W R/W
15 14 13
0 0 0
R/W R/W R/W
7 6 5
0 0 0
R/W R/W R/W
Section 7 DMA Controller (DMAC)
28 27 26
0 0 0
R/W R/W R/W
20 19 18
0 0 0
R/W R/W R/W
12 11 10
0 0 0
R/W R/W R/W
4 3 2
0 0 0
R/W R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 139 of 804
25 24
0 0
R/W R/W
17 16
0 0
R/W R/W
9 8
0 0
R/W R/W
1 0
0 0
R/W R/W
REJ09B0104-0300