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Table 17.3 Registers/Parameters and Target Modes
Register/Parameter
Programming/
FCCS
erasing interface
FPCS
registers
FECS
FKEY
FMATS
FTDAR
Programming/
DPFR
erasing interface
FPFR
parameters
FPEFEQ
FMPAR
FMPDR
FEBS
RAM emulation
RAMER
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target memory MAT.
17.7.1
Programming/Erasing Interface Registers
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes.
These registers are initialized by a power-on reset.
(1)
Flash Code Control/Status Register (FCCS)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip
program to be downloaded to the on-chip RAM.
Bit
7
Bit Name
—
Initial Value
1
R/W
R
Down-
Initiali-
load
zation
O
O
O
O
O
O
O
O
6
5
4
—
—
FLER
0
0
0
R
R
R
Section 17 Flash Memory (0.18-(m F-ZTAT Version)
Program-
ming
Erasure
O
O
1
1
O*
O*
O
O
O
O
O
3
2
—
—
0
0
R
R
Rev. 3.00 Mar. 14, 2006 Page 579 of 804
RAM
Read
Emulation
2
O*
O
1
0
—
SCO
0
0
R
(R)/W
REJ09B0104-0300
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