Instruction Exception Handling; Trap Instruction; Table 4.8 Status Of Ccr And Exr After Trap Instruction Exception Handling - Renesas H8SX/1520 Series Hardware Manual

4.7

Instruction Exception Handling

There are two types of instructions that cause exception handling: trap instruction and illegal
instructions.
4.7.1

Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state. The trap
instruction exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the vector number specified in
the TRAPA instruction is generated, the start address of the exception service routine is loaded
from the vector table to PC, and program execution starts from that address.
A start address is read from the vector table corresponding to a vector number from 0 to 3, as
specified in the instruction code.
Table 4.8 shows the state of CCR and EXR after execution of trap instruction exception handling.
Table 4.8
Interrupt Control Mode
0
2
[Legend]
1: Set to 1
0: Cleared to 0
:
Retains the previous value.
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Status of CCR and EXR after Trap Instruction Exception Handling
I
1
1
CCR
UI T
 

0
Rev. 3.00 Mar. 14, 2006 Page 83 of 804
Section 4 Exception Handling
EXR
I2 to I0


REJ09B0104-0300