Multi-Clock Function; Module Stop Mode - Renesas H8SX/1500 Series Hardware Manual

19.3

Multi-Clock Function

When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, a transition is
made to multi-clock mode at the end of the bus cycle. In multi-clock mode, the CPU and bus
masters operate on the operating clock specified by bits ICK2 to ICK0. The peripheral modules
operate on the operating clock specified by bits PCK2 to PCK0. The external bus operates on the
operating clock specified by bits BCK2 to BCK0.
Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the
frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral
module and external bus clocks. The peripheral module and external bus clocks are restricted to
the operating clock specified by bits ICK2 to ICK0.
Multi-clock mode is cleared by clearing all of bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to
BCK0 to 0. A transition is made to normal mode at the end of the bus cycle, and multi-clock mode
is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, this LSI enters
sleep mode. When sleep mode is cleared by an interrupt, multi-clock mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, this LSI enters
software standby mode. When software standby mode is cleared by an external interrupt, multi-
clock mode is restored.
When the RES pin is driven low, the reset state is entered and multi-clock mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
19.4

Module Stop Mode

Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module
operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU
continues operating independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI, HCAN and SSU are retained.
After the reset state is cleared, all modules other than the DMAC and on-chip RAM are in module
stop mode.
Section 19 Power-Down Modes
Rev. 3.00 Mar. 14, 2006 Page 679 of 804
REJ09B0104-0300