Figure 12.16 Example Of Operation For Transmission In Clocked Synchronous Mode; Figure 12.17 Sample Serial Transmission Flowchart - Renesas H8SX/1520 Series Hardware Manual

Synchronization
clock
Serial data
TDRE
TEND

Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode

Downloaded from Elcodis.com electronic components distributor
Transfer direction
Bit 0
TXI interrupt Data written to TDR
request generated and TDRE flag cleared
to 0 in TXI interrupt
processing routine
Initialization
Start transmission
Read TDRE flag in SSR
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
All data transmitted
Yes
Read TEND flag in SSR
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>

Figure 12.17 Sample Serial Transmission Flowchart

Section 12 Serial Communication Interface (SCI)
Bit 1 Bit 7 Bit 0
TXI interrupt
request generated
1 frame
[1] SCI initialization:
[1]
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI state check and transmit data
[2] write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
No
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0. However, the TDRE
No
flag is checked and cleared
[3]
automatically when the DMAC is
initiated by a transmit data empty
interrupt (TXI) request and writes data
to TDR.
No
Bit 1 Bit 6 Bit 7
TEI interrupt request
generated
Rev. 3.00 Mar. 14, 2006 Page 425 of 804
REJ09B0104-0300