Figure 7.38 Interrupt And Interrupt Sources; Figure 7.39 Procedure Example Of Resuming Transfer By Clearing Interrupt Source - Renesas H8SX/1520 Series Hardware Manual

Section 7 DMA Controller (DMAC)
TSIE bit
DMAC is activated in
transfer size error state
RPTIE bit
DMAC is activated
after BKSZ bits are
changed from 1 to 0
SARIE bit
Extended repeat area
overflow occurs in
source address
DARIE bit
Extended repeat area
overflow occurs in
destination address
[1] Specify the values in the registers such as transfer counter and address register.
[2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or
ESIF bit in DMDR to 0 and an interrupt source is cleared.
[3] End the interrupt handling routine by the RTE instruction.
[4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit.
[5] Complete the interrupt handling routine and clear the interrupt mask.
[6] Specify the values in the registers such as transfer counter and address register.
[7] Set the DTE bit to 1 to resume DMA operation.

Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source

Rev. 3.00 Mar. 14, 2006 Page 202 of 804
REJ09B0104-0300
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Figure 7.38 Interrupt and Interrupt Sources

Transfer end interrupt
handling routine
Consecutive transfer
processing
Registers are specified
DTE bit is set to 1
Interrupt handling routine
ends (RTE instruction
executed)
Transfer resume
processing end
DTIE bit
DTIF bit
ESIE bit
ESIF bit
Setting condition is satisfied
Transfer resumed after
interrupt handling routine
[1]
DTIF and ESIF bits are
cleared to 0
[2]
Interrupt handling routine
[3]
Registers are specified
DTE bit is set to 1
Transfer resume
processing end
[Setting condition]
When DTCR becomes 0
and transfer ends
[4]
[5]
ends
[6]
[7]
Transfer end
interrupt
Transfer escape
end interrupt