Figure 14.9 Flowchart Example Of Simultaneous Transmission/Reception (Ssu Mode) - Renesas H8SX/1520 Series Hardware Manual

[1]
[2]
Write transmit data to SSTDR
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
[3]
No
Read receive data in SSRDR
RDRF automatically cleared
Clear TEND in SSSR to 0
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.

Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)

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Start
Initial setting
Read TDRE in SSSR
TDRE = 1?
Yes
Read SSSR
RDRF = 1?
Yes
ORER = 1?
No
Consecutive data
transmission/reception?
No
Read TEND in SSSR
TEND = 1?
Yes
Has the 1 bit transfer
period elapsed?
Yes
Section 14 Synchronous Serial Communication Unit (SSU)
[1] Initial setting:
Specify the transmit/receive data format.
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
No
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
[4]
Yes
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
[5]
Yes
No
Error processing
No
Rev. 3.00 Mar. 14, 2006 Page 537 of 804
REJ09B0104-0300