Figure 7.5 Example Of Signal Timing In Single Address Mode; Figure 7.6 Operations In Single Address Mode - Renesas H8SX/1500 Series Hardware Manual

Transfer from external memory to external device with DACK
Bφ
Address bus
RD
WR
DACK
Data bus
TEND
Transfer from external device with DACK to external memory
Bφ
Address bus
RD
WR
DACK
Data bus
TEND

Figure 7.5 Example of Signal Timing in Single Address Mode

Address T
Address B

Figure 7.6 Operations in Single Address Mode

DMA cycle
DSAR
DMA cycle
DDAR
Transfer
Section 7 DMA Controller (DMAC)
Address for external memory space
RD signal for external memory space
Data output by external memory
Address for external memory space
WR signal for external memory space
Data output by external device with DACK
Rev. 3.00 Mar. 14, 2006 Page 161 of 804
DACK
REJ09B0104-0300