Ss Shift Register (Sstrsr); Table 14.3 Correspondence Between Dats Bit Setting And Ssrdr - Renesas H8SX/1520 Series Hardware Manual

Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W

Table 14.3 Correspondence Between DATS Bit Setting and SSRDR

SSRDR
0
1
2
3
14.3.9

SS Shift Register (SSTRSR)

SSTRSR is a shift register that transmits and receives serial data.
When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR
contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB
first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to
perform serial data transmission.
In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB
(bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to
SSRDR. SSTRSR cannot be directly accessed by the CPU.
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7 6
0 0
R R
7 6
0 0
R R
7 6
0 0
R R
7 6
0 0
R R
00 01
Valid Valid
Invalid Valid
Invalid Invalid
Invalid Invalid
Section 14 Synchronous Serial Communication Unit (SSU)
5 4 3
0 0 0
R R R
5 4 3
0 0 0
R R R
5 4 3
0 0 0
R R R
5 4 3
0 0 0
R R R
DATS[1:0] (SSCRL[1:0])
10
Valid
Valid
Valid
Valid
2 1
0 0
R R
2 1
0 0
R R
2 1
0 0
R R
2 1
0 0
R R
11 (Setting Invalid)
Invalid
Invalid
Invalid
Invalid
Rev. 3.00 Mar. 14, 2006 Page 525 of 804
REJ09B0104-0300
0
0
R
0
0
R
0
0
R
0
0
R