Figure 9.16 Example Of Buffer Operation (1) - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer

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Examples of Buffer Operation

When TGR is an output compare register

Figure 9.16 shows an operation example in which PWM mode 1 has been designated for channel

0, and buffer operation has been designated for TGRA and TGRC. The settings used in this

example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at

compare match B.

As buffer operation has been set, when compare match A occurs, the output changes and the value

in buffer register TGRC is simultaneously transferred to timer general register TGRA. This

operation is repeated each time compare match A occurs.

For details on PWM modes, see section 9.4.5, PWM Modes.

Figure 9.16 Example of Buffer Operation (1)

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Mar. 14, 2006 Page 309 of 804

REJ09B0104-0300

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