Interrupt Mask Register (Imr) - Renesas H8SX/1500 Series Hardware Manual

13.3.13 Interrupt Mask Register (IMR)

IMR enables or disables interrupt requests by IRR interrupt flags. The reset interrupt flag cannot
be masked.
Bit 15
Bit Name IMR7
Initial Value 1
R/W R/W
Bit 7
Bit Name —
Initial Value 1
R/W R
Bit Bit Name
15 IMR7
14 IMR6
13 IMR5
12 IMR4
11 IMR3
14 13
IMR6 IMR5
1 1
R/W R/W
6 5
— —
1 1
R R
Initial
Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Section 13 Controller Area Network (HCAN)
12 11
IMR4 IMR3 IMR2
1 1
R/W R/W R/W
4 3
IMR12 —
1 1
R/W R
Description
Overload Frame Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR7 (OVR0) is enabled. When set to 1, it is
masked.
Bus Off Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR6 (ERS0) is enabled. When set to 1, it is
masked.
Error Passive Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR5 (ERS0) is enabled. When set to 1, it is
masked.
Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR4 (OVR0) is enabled. When set to 1, it is
masked.
Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR3 (OVR0) is enabled. When set to 1, it is
masked.
Rev. 3.00 Mar. 14, 2006 Page 471 of 804
10 9 8
IMR1 —
1 1 0
R
R/W
2 1 0
— IMR9 IMR8
1 1 1
R R/W R/W
REJ09B0104-0300