Priority Of Channels; Figure 7.22 Example Of Timing For Channel Priority; Table 7.5 Priority Among Dmac Channels - Renesas H8SX/1500 Series Hardware Manual

7.4.8

Priority of Channels

The channels of the DMAC are given following priority levels: channel 0 > channel 1 >
channel 2 > channel3. Table 7.5 shows the priority levels among the DMAC channels.
Table 7.5 Priority among DMAC Channels
Channel
Channel 0
Channel 1
Channel 2
Channel 3
The channel having highest priority other than the channel being transferred is selected when a
transfer is requested from other channels. The selected channel starts the transfer after the channel
being transferred releases the bus. At this time, when a bus master other than the DMAC requests
the bus, the cycle for the bus master is inserted.
In a burst transfer or a block transfer, channels are not switched.
Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2.
Bφ
Address bus
DMAC
Wait
operation
Channel 0
Channel 1
Request
retained
Channel 2
Request
retained
Channel 0 transfer
Channel 0
Channel 0
Request cleared
Request cleared
Selected
Not Request
selected retained

Figure 7.22 Example of Timing for Channel Priority

Channel 1 transfer
Bus
Channel 1
released
Channel 1 Channel 2
Request cleared
Selected
Rev. 3.00 Mar. 14, 2006 Page 181 of 804
Section 7 DMA Controller (DMAC)
Priority
High
Low
Channel 2 transfer
Bus
Channel 2
released
Wait
REJ09B0104-0300