Section 5 Interrupt Controller; Features - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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• Two interrupt control modes

Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the

interrupt control register (INTCR).

• Priority can be assigned by the interrupt priority register (IPR)

IPR provides for setting interrupt priory. Eight levels can be set for each module for all

interrupts except for the interrupt requests listed below. The following six interrupt requests

are given priority of 8, therefore they are accepted at all times.

 General illegal instructions

 Trap instructions

 CPU address error

 DMA address error*

• Independent vector addresses

All interrupt sources are assigned independent vector addresses, making it unnecessary for the

source to be identified in the interrupt handling routine.

• 16 external interrupts

NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge

detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level

sensing, can be selected for IRQ14 to IRQ0.

• DMAC control

DMAC can be activated by means of interrupts.

• CPU priority control function

The priority levels can be assigned to the CPU and DMAC. The priority level of the CPU can

be automatically assigned on an exception generation. Priority can be given to the CPU

interrupt exception handling over that of the DMAC transfer.

Note: * A DMA address error is generated within the DMAC.

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Section 5 Interrupt Controller

Rev. 3.00 Mar. 14, 2006 Page 87 of 804

REJ09B0104-0300

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