Table 4.6 shows the states of CCR and EXR after the address error exception handling.
Table 4.6
States of CCR and EXR after Address Error Exception Handling
Interrupt Control Mode I
0
2
[Legend]
1:
Set to 1.
0:
Cleared to 0.
:
Retains the previous value.
4.6
Interrupts
4.6.1
Interrupt Sources
Interrupt sources are NMI, IRQ0 to IRQ14, and on-chip peripheral modules, as shown in table 4.7.
Table 4.7
Interrupt Sources
Type
Source
NMI
NMI pin (external input)
Pins IRQ0 to IRQ11 (external input)
IRQ0 to IRQ14
On-chip
Watchdog timer (WDT)
peripheral
A/D converter
module
16-bit timer pulse unit (TPU)
DMA controller (DMAC)
Serial communications interface (SCI)
Synchronous serial communication unit (SSU)
Controller area network (HCAN)
Notes: 1. The number of interrupts for the H8SX/1527
2. The number of interrupts for the H8SX/1525
Different vector numbers and vector table offsets are assigned to different interrupt sources. For
vector number and vector table offset, refer to table 5.2 in section 5.5, Interrupt Exception
Handling Vector Table.
CCR
UI
1
1
Section 4 Exception Handling
EXR
T
I2 to I0
0
7
Number of Sources
1
15
1
2
1
2
52*
/26*
8
8
9
4
Rev. 3.00 Mar. 14, 2006 Page 81 of 804
REJ09B0104-0300