Receive Complete Register (Rxpr) - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer
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13.3.9

Receive Complete Register (RXPR)

RXPR indicates the normal reception of messages (data frame or remote frame) in mailboxes. For
reception of a remote frame, when a bit in this register is set to 1, the corresponding remote
request register (RFPR) bit is also set to 1 simultaneously.
Bit
15
Bit Name
RXPR7
Initial Value
0
R/W
R/(W)*
Bit
7
Bit Name
RXPR15
Initial Value
0
R/W
R/(W)*
Note: *
Only 1 can be written to these bits, to clear the flags.
Bit
Bit Name
15
RXPR7
14
RXPR6
13
RXPR5
12
RXPR4
11
RXPR3
10
RXPR2
9
RXPR1
8
RXPR0
7
RXPR15
6
RXPR14
5
RXPR13
4
RXPR12
3
RXPR11
2
RXPR10
1
RXPR9
0
RXPR8
Note:
Only 1 can be written to clear the flag.
*
14
13
RXPR6
RXPR5
RXPR4
0
0
R/(W)*
R/(W)*
6
5
RXPR14
RXPR13
RXPR12
0
0
R/(W)*
R/(W)*
Initial
Value
R/W
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
Section 13 Controller Area Network (HCAN)
12
11
RXPR3
RXPR2
0
0
R/(W)*
R/(W)*
R/(W)*
4
3
RXPR11
RXPR10
0
0
R/(W)*
R/(W)*
R/(W)*
Description
When the message in mailbox n (n = 1 to 15) has
been received error-free, RXPRn is set to 1.
[Setting condition]
Completion of message (data frame or remote
frame) reception in corresponding mailbox
[Clearing condition]
Writing 1
Rev. 3.00 Mar. 14, 2006 Page 463 of 804
10
9
8
RXPR1
RXPR0
0
0
0
R/(W)*
R/(W)*
2
1
0
RXPR9
RXPR8
0
0
0
R/(W)*
R/(W)*
REJ09B0104-0300

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