Figure 14.7 Example Of Reception Operation (Ssu Mode) - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer
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(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
SCS
SSCK
SSI
RDRF
LSI operation
User operation
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
SCS
SSCK
SSI
(LSB first)
SSI
(MSB first)
RDRF
LSI operation
User operation
(3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0
SCS
SSCK
SSI
(LSB first)
SSI
(MSB first)
RDRF
LSI operation
User operation
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1 frame
Bit
Bit
Bit
Bit
0
1
2
3
SSTDR0 (LSB first transmission)
Dummy-read SSRDR0
Bit
Bit
Bit
Bit
0
1
2
3
SSRDR1
Bit
Bit
Bit
Bit
7
6
5
4
SSRDR0
Dummy-readSSRDR0
Bit
Bit
Bit
to
0
7
0
SSRDR3
SSRDR2
Bit
Bit
Bit
to
7
0
7
SSRDR0
SSRDR1
Dummy-readSSRDR0

Figure 14.7 Example of Reception Operation (SSU Mode)

Section 14 Synchronous Serial Communication Unit (SSU)
Bit
Bit
Bit
Bit
Bit
4
5
6
7
7
RXI interrupt
generated
Read SSRDR0
1 frame
Bit
Bit
Bit
Bit
Bit
Bit
Bit
4
5
6
7
0
1
2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
3
2
1
0
7
6
5
Bit
Bit
Bit
Bit
to
to
to
7
0
7
0
SSRDR1
SSRDR0
Bit
Bit
Bit
Bit
to
to
to
0
7
0
7
SSRDR2
SSRDR3
RXI interrupt generated
Rev. 3.00 Mar. 14, 2006 Page 535 of 804
1 frame
Bit
Bit
Bit
Bit
Bit
Bit
Bit
6
5
4
3
2
1
0
SSTDR0 (MSB first transmission)
RXI interrupt
generated
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
SSRDR0
Bit
Bit
Bit
Bit
Bit
4
3
2
1
0
SSRDR1
RXI interrupt generated
Bit
7
Bit
0
REJ09B0104-0300

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