Operation; Hardware And Software Resets; Initialization After Hardware Reset - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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Section 13 Controller Area Network (HCAN)

Operation

The HCAN can be reset by a hardware reset or software reset.

• Hardware Reset

At power-on reset or a transition to software standby mode, the HCAN is initialized by

automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3)

in GSR. At the same time, all internal registers, except for message control and message data

registers, are initialized by a hardware reset.

• Software Reset

The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In

a software reset, the error counters (TEC and REC) are initialized, however other registers are

not. If bit MCR0 is set while the CAN controller is performing a communication operation

(transmission or reception), the initialization state is not entered until message transfer has

been completed. The reset status bit (GSR3) in GSR is set on completion of initialization.

After a hardware reset, the following initialization processing should be carried out:

1. Clearing of bit IRR0 in the interrupt register (IRR)

2. Bit rate setting

3. Mailbox transmit/receive settings

4. Mailbox (RAM) initialization

5. Message transmission method setting

These initial settings must be made while the HCAN is in bit configuration mode. Configuration

mode is a state in which bit GSR3 in GSR is set to 1 by a reset. Configuration mode is exited by

clearing bit MCR0 in MCR to 0; when bit MCR0 is cleared to 0, the HCAN automatically clears

bit GSR3 in GSR. There is a delay between clearing bit MCR0 and clearing bit GSR3 because the

HCAN needs time to be internally reset. After the HCAN exits configuration mode, the power-up

sequence begins, and communication with the CAN bus is possible as soon as 11 consecutive

recessive bits have been detected.

Rev. 3.00 Mar. 14, 2006 Page 484 of 804

REJ09B0104-0300

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